Your car, your cell phone, your LED holiday lights, even your credit card – all of them contain electronic chips made of semiconductors. These materials manipulate the flow of electricity and provide the foundation for modern electronics.
Over the years, American investment in this essential technology has lagged, but the federal CHIPS and Science Act seeks to reinvigorate it. Passed in 2022, this legislation provides the U.S. Department of Commerce with $52 billion to spend on the semiconductor sector. To administer this effort’s research and development component, the department has created the National Semiconductor Technology Center (NSTC), a consortium drawn from academia, industry, government, and nonprofits. In November, Stanford joined the NSTC as an academic institution conducting semiconductor-related research.
In a Q&A with Stanford Report, H.-S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering, explains what NSTC membership means for Stanford and how it builds on an institutional legacy of leadership in this field.
H.S. Philip Wong | Courtesy Stanford School of Engineering
Why is the U.S. increasing investments in semiconductor research and development?
The semiconductor is a foundational technology that underpins many technological advances, and economists recognize advances in technology as the most important driving force for economic development.
The U.S. also recognizes that this is important to national security. Semiconductor technologies that are vital to the daily functioning of our country and the people who live in it depend on chips, as with anywhere in the world. We’ve seen that during the pandemic – the lack of chips brought the auto industry to a grinding halt.
We should always be able to secure our supply of chips. In order to do that, we should a) work with like-minded allies and build a robust manufacturing ecosystem in the U.S. and like-minded countries and regions, and b) do the research and development so we can continue to put out new generations of chips.
What has Stanford’s role been in semiconductor research?
To do research and make chips, you need the equivalent of a kitchen. Prior to the 1980s, individual professors needed to have their own kitchen. But that changed when Stanford, in the early ’80s, pioneered this concept of a shared facility that lowers the cost of chip research and becomes a gathering place for researchers to generate ideas. Just like the knowledge of how to cook, knowledge about how to make chips can be shared. We now have two complementary facilities to support our researchers: the Stanford Nanofabrication Facility and the Stanford Nano Shared Facilities.
Stanford has also produced technology the industry currently uses to develop and manufacture chips, such as the simulation and modeling tools that Stanford professors Jim Plummer and Robert Dutton developed. There are many more examples of research at Stanford that made its way into the industry and has enormous impact.
How will Stanford benefit from the NSTC membership?
NSTC will award millions in sponsored research grants, and to tap into that funding, you need to be a member of the consortium. Stanford chose to become a member because we want to participate in the research, not only to access those competitive resources but, most importantly, to interact with the broader community.
The NSTC will establish three main facilities, two of which have been announced. As members, we have access to all these facilities.
The first facility in New York will provide services for one of the steps of fabrication, namely, lithography [in which a circuit pattern is transferred onto the silicon wafer that will become the chip].
The second facility will be in California, in nearby Sunnyvale. It will serve as the administrative headquarters of the NSTC, and within the same facility, there will be a design research center. This location was chosen through great efforts from local companies, as well as Stanford and the University of California, Berkeley, and other university partners advocating for that site. It will greatly benefit Stanford research because many faculty are doing research on the design of chips.
The one yet to be announced is like the Stanford nanofabrication facility but at an industrial scale – bigger, more industry-oriented, more fancy tools, and so on.
What research is out there now that has exciting implications for future generations of chips?
Chips have always been in two dimensions. We’ve been working on this concept of making three-dimensional chips.
The more transistors [nanometer-scale electrical switches] that we have on a chip, the more functional and energy efficient it becomes. We have been asking: How do we squeeze more transistors onto a tiny chip? Now it gets to a point where the house is so small people don’t want to live in it anymore. How do you get more living space? Well, go on to the third dimension. Instead of cramming more into a single-story house, build taller buildings, Manhattan-style.
Making skyscrapers in place of 2D houses is a new type of challenge. The NSTC facilities, particularly the design research center, will help with this challenge.
What advantages could these three-dimensional chips have over existing technologies?
You’ve probably heard that people are interested in building big data centers to train AI models. You’ve probably also heard that those big data centers will use a lot of energy and that companies need nuclear power plants. Obviously, it’s not scalable. The new generation of chips should aim to reduce energy consumption for those types of applications.
The new chips will also improve functionality. Look at your phone. Your phone today does a lot more things than your phone did 10 years ago. Improvements in chips made that possible.