8/26/96
CONTACT: Stanford University News Service (650) 723-2558
STANFORD -- As computer chips grow larger and more complex and are driven at ever higher speeds, manufacturers face increasing difficulty in identifying defective chips. Stanford's Center for Reliable Computing (SCRC) and the specialty chip maker LSI Logic Corporation of Milpitas now have embarked on a three-year, $400,000 effort to improve chip testing methods.
Ten years ago, a single integrated circuit contained thousands of transistors operating at a few million cycles per second. Today, integrated circuits carry tens of millions of transistors and operate at hundreds of millions of cycles per second. Ten years from now, they are expected to pack hundreds of billions of transistors operating at billions of cycles per second.
In the past, manufacturers have approached the test problem by building bigger and faster electronic testers. But this strategy is becoming prohibitively expensive, says E. J. McCluskey, director of the reliable computing center and professor of electrical engineering and computer science.
McCluskey and his colleagues have opted instead to develop improved testing methods, and in the joint project with LSI Logic will evaluate the effectiveness of more than two dozen test techniques.
"We have designed and built an integrated circuit whose only point in life is to be tested. We will test it in lots of different ways. In this way we hope to demonstrate, for example, that one procedure detects 80 percent of the defects, while another procedure detects 99 percent," McCluskey said.
The study will evaluate methods that test all aspects of state-of-the-art integrated circuit performance including logic, memory and other mixed signal circuits. The study also will explore several advanced testing procedures, such as design-for-test and built-in self-test techniques.
McCluskey is principal investigator on the project. Electrical engineering graduate student Jonathan (Tsung-Yung) Chang is the project leader. LSI Logic managers are Nick Sporck, project engineering manager, and Mike Lynch, manager of the Design Tools Group.
-dfs-
960826chiptest.html
Download this release and its related files.
The release is provided in Adobe Acrobat format. Any images shown in the release are provided at publishing quality. Additional images also may be provided. Complete credit and caption information is included.
960826chiptest.sit