CONTACT: Stanford University News Service (650) 723-2558
Cost of designing chips to dip with 'virtual factory'
STANFORD -- By the end of the decade, designers will use a high-performance computer simulation to design, "build" and test a complex computer chip in a tiny fraction of the time now required, says a researcher who is pioneering the way.
"It will make it transparent to the designer whether he or she is simulating devices or actually making them," said Robert Dutton, a professor of electrical engineering at Stanford.
For a chip designer, this "virtual factory" will mean the power to push the limits of integrated-circuit design, boosting competitiveness and productivity by saving time and money.
Speaking Monday, Feb. 10, to the annual meeting of the American Association for the Advancement of Science in Chicago, Dutton described his research group's work on a new generation of 3-D integrated-circuit simulations that will be used to develop tomorrow's denser, more powerful computer chips. The work - using some of today's fastest parallel computers to design applications for still faster machines - is supported by the Defense Advanced Research Projects Agency and by Comtech, the State of California's competitive technology program.
So far, 3-D models require too much computer power to be broadly used in industry. At AAAS, Dutton described a three-dimensional simulation of an advanced bipolar transistor that involved perhaps the most complex non-linear problem solved to date: the calculation took 12 hours of 1.7 GigaFLOPS computations - that's 1 billion, 700 million floating-point operations per second.
Such a task could be done in seconds by the "TeraOPS" (trillions of operations per second) massively parallel computers that are the late '90s goal of the federal government's High Performance Computing and Communications initiative, Dutton said. And that would bring to the factory floor some of the simulations that Dutton's team is now producing in the lab.
In 1977, Dutton's research team introduced SUPREM, the first comprehensive computerized process simulation of essential steps in integrated circuit production. The program, now in its fourth generation, predicts the behavior of the complex, interacting layers of materials on a chip.
Executives from Intel and Advanced Micro Devices have independently told Dutton that such process modeling cuts in half the cost of designing a new set of chip-manufacturing steps and the time it takes to get the new design into production. That means millions of dollars and competitive advantage.
Such simulations show two things: how the patterns on a chip will "grow" during manufacture, and how electrical current will flow in the finished chip. Electrons flowing into undesired areas can create errors, and can trigger "latchup," in which current spreads from device to device and causes a catastrophic short in the computer's power supply.
As computer chips get progressively smaller and more complex - the lines and spaces on a chip are now as small as 1/4 micron, 300 times thinner than a human hair - it becomes more difficult to isolate transistors from one another. To avoid latchup, designers must consult thick volumes of design rules.
Dutton's 3-D color models, though, instantly visualize both the chip's shape and its electrical properties, and free the designer to quickly "move" parts around, testing which configuration is most resistant to latchup.
This is an archived release.
This release is not available in any other form.
Images mentioned in this release are not available online.