Stanford University News Service
425 Santa Teresa Street
Stanford, California 94306-2245
Tel: (650) 723-2558
Fax: 650) 725-0247
http://news.stanford.edu


News Release

August 24, 2009

Contact:

Dan Stober, News Service: (650) 721-6965, dstober@stanford.edu

Stanford researchers grow nanowire crystals for 3-D microchips

Stanford researchers have developed a method of stacking and crystalline semiconductor layers that sets the potential for three-dimensional microchips.

The scientists added tiny growing crystals called nanowires to a sheet of silicon, and then topped it off with a layer of non-crystalline (amorphous) germanium. With heat, the nanowires, which have the same internal structure as that of the silicon, transformed the amorphous germanium layer into a perfect crystal. Integrating germanium onto silicon is a difficult process that is important for fabricating future, three-dimensional integrated circuits, on microchips.

“We can make very long and very small single crystal nanowires and, in principal, place them where they are needed on a surface,” said Paul McIntyre, director of the Geballe Laboratory for Advanced Materials at Stanford and one of the four researchers on the project. “We use them as seeds to crystallize initially non-crystalline layers on top of the level of silicon and, therefore, control the perfection and orientation of those overlying layers.”

To function well, microchips require crystals that have perfectly arranged atoms. Groups at Stanford and around the world are looking for ways to combine multiple crystal layers onto one chip. A multiple-layer chip is one approach to building a three-dimensional integrated circuit, which would contain densely packed conductors that produce more computing and communication functionality per unit of surface area. Three-dimensional chips also benefit from shorter electron pathways that allow electrical current to flow with less resistance.

The challenge is to build crystals that conduct electricity efficiently, but are small enough to layer densely onto a microchip. “Many scientific groups are trying to find a new semiconductor switch, beyond the transistor, that will have more computing power, higher speed, lower energy consumption, and could continue to scale down for many years to come,” McIntyre said. An alternative approach is to stack new devices on top of an array of transistors built on silicon, hence the interest in 3D circuits.

To create a stack of crystal layers used on a microchip, “we have tried to find a clever way, using nanowires, to deposit a layer that isn’t a single crystal and then to crystallize it so that it shares the perfect orientation of the silicon substrate,” McIntyre said.

The group’s unique approach starts with a layer of silicon crystal. Tiny crystal wires made of germanium are placed on the silicon and grow vertically-upward for lengths of several millionths of a meter. They’re coated with silicon dioxide and a glassy layer of germanium. When heated, the crystalline structure from the underlying silicon is transferred via the nanowires to the overlying germanium layer and its initially disordered atoms become perfectly arranged.

In principle, an unlimited number of stacked crystal layers can be fabricated on silicon to create devices densely interconnected with nanowires. “Producing a potential electrical connection through the nanowire is very interesting. The ability to access each of these devices individually from layer to layer in an easy way is one thing that many people would like to have,” McIntyre said.

The group, which also includes graduate student Shu Hu, former student Dr. Paul Leu and research associate Dr. Ann Marshall, published their results in Nature Nanotechnology.

-30-

Comment:

Paul McIntyre, Materials Science and Engineering: (650) 725-9806, pcm1@stanford.edu

Related Information:

To subscribe to our news releases:

Email news-service@lists.stanford.edu or phone (650) 723-2558.