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News Release

February 13, 2008

Contact:

David Orenstein, School of Engineering: (650) 736-2245, davidjo@stanford.edu


Engineers demonstrate nanotube wires operating at speed of commercial chips

Integrated circuits, such as the silicon chips inside all modern electronics, are only as good as their wiring, but copper conduits are approaching physical performance limitations as they get thinner. Chipmakers have hoped that carbon "nanotubes" would allow them to continue using thinner wiring as they pack more devices into chips, but no one had demonstrated nanotube wires working on a conventional silicon chip. In a paper published online today by the journal Nano Letters, electrical engineers at Stanford University and Toshiba report using nanotubes to wire a silicon chip operating at speeds comparable to those of commercially available processors and memory.

"This is the first time anyone has been able to show digital signals going through nanotubes at 1 gigahertz [a billion times a second]," said H.-S. Philip Wong, a professor of electrical engineering at Stanford and a co-author of the report. "There had been a lot of expectations that nanotubes could do this, but no experimental proof so far."

At stake is the continuation of the famous Moore's Law, which calls for doubling the number of transistors on a chip every two years. The increase in transistors correlates strongly with greater computing power but also requires thinner and thinner wiring. The advance reported by the Stanford and Toshiba team shows that nanotubes are capable not only of connecting transistors at industrially relevant speed but of doing so in real circuits that use materials, designs and manufacturing processes compatible with those that chipmakers use today, added Gael Close, an electrical engineering doctoral student and the paper's lead author.

Joining Close and Wong in the research were Shinichi Yasuda and Shinobu Fujita of Toshiba's Advanced Semiconductor Laboratory in Japan and Bipul Paul of Toshiba America Research in San Jose.

The silicon chip Close and his collaborators built is an array of 256 circuits called "ring oscillators," which are industry-standard circuits for testing the speed of chips. Including other control circuitry that allowed for selectively operating each of the 256 oscillators, the chip comprised a total of 11,000 transistors in an area one hundredth of a square inch.

When designing the chip, Close, Wong and the Toshiba researchers purposely left one wire of each oscillator unconnected so the circuit is not completely wired up. After the semiconductor foundry TSMC made the chip, Close then engaged in a few more fabrication steps at the Stanford Nanofabrication Facility to complete the missing connections with the nanotubes. Each nanotube measured between 50 and 100 nanometers (billionths of a meter) in diameter and about 5 millionths of a meter in length.

The nanotubes, purchased from a commercial vendor, were "metallic" in that they were synthesized for maximum electrical conductivity.

The quality of the nanotubes and their connections varied widely, but in the end 19 of the ring oscillators were successfully connected. The nanotubes rested directly above the transistors they were connecting, minimizing electrical capacitance and allowing for the transmission of zeroes and ones at 1.02 gigahertz, or billions of times a second, in the best case. In 16 of the 19 good connections, the oscillators ran at speeds better than 800 megahertz, or millions of cycles a second.

The processors in personal computers currently on the market run at speeds between 2 and 3 gigahertz. The processor in an iPhone reportedly runs at about 700 megahertz.

Consumers should not expect the research to mean that they'll be putting nanotubes in their pockets next year, the researchers cautioned. Many improvements are needed for nanotube wiring to enter commercial use, Wong said, including more consistent nanotube purity and size, and more reliably made connections. The nanotubes in Close's chip were about the same size as the copper wires used today. Transmission of even higher-frequency signals in even thinner nanotubes will require improvements in both nanotube quality and circuit design.

But Wong and Close both said the research provides the most definitive confirmation to date that nanotubes can be the heir apparent to copper that the industry needs.

"This is a significant step but it is still very much at the proof of concept level," Close said. "The industry has been waiting for this kind of a demonstration to really move forward."

In addition to Toshiba, support for the research came from the semiconductor industry's Interconnect Focus Center, one of five research centers funded under the Focus Center Research Program, which is a Semiconductor Research Corporation program; and Close's Intel Graduate Fellowship.

David Orenstein is the communications and public relations manager at the Stanford School of Engineering.

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Comment:

H.-S. Philip Wong, Electrical Engineering: (650) 725-0982, hspwong@stanford.edu

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